`include "cpu_def.vh"

module debug(
  input [31:0] pc_i,
  input        rf_wen_i,
  input [ 4:0] rf_wnum_i,
  input [31:0] rf_wdata_i,

  output [31:0] debug_wb_pc      ,
  output [ 3:0] debug_wb_rf_wen  ,
  output [ 4:0] debug_wb_rf_wnum ,
  output [31:0] debug_wb_rf_wdata
);

  assign debug_wb_pc       = pc_i         ;
  assign debug_wb_rf_wen   = {4{rf_wen_i}};
  assign debug_wb_rf_wnum  = rf_wnum_i    ;
  assign debug_wb_rf_wdata = rf_wdata_i   ;

endmodule